參數(shù)資料
型號： MC56F8356MFVE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝： ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 58/178頁
文件大?。?/td> 910K
代理商： MC56F8356MFVE
56F8356 Technical Data, Rev. 13
150
Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
RD Deasserted to RD Asserted
tRDRD
-0.2342
0.00
RWSS,RWSH
MDAR3, 4
ns
WR Deasserted to WR Asserted
tWRWR
WWS=0
-1.279
0.75 + DCAEO
WWSS, WWSH
ns
WWS>0
-0.938
1.00
RD Deasserted to WR Asserted
tRDWR
WWS=0
-0.046
0.50
RWSH, WWSS,
MDAR3
ns
WWS>0
0.052
0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is acive in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration
tRA
16T
—
ns
RESET Deassertion to First External Address
Output3
tRDA
63T
64T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM
18T
—
ns
tIDM - FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG - FAST
14T
—
Delay from IRQA Assertion (exiting Wait) to
External Data Memory Access4
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
tIF
22T
—
ns
tIF - FAST
18T
—
Table 10-16 External Memory Interface Timing (Continued)
Characteristic
Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
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