參數(shù)資料
型號: MC56F8356MFVE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: ROHS COMPLIANT, LQFP-144
文件頁數(shù): 53/178頁
文件大?。?/td> 910K
代理商: MC56F8356MFVE
56F8356 Technical Data, Rev. 13
146
Freescale Semiconductor
Preliminary
10.5 External Clock Operation Timing
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
Table 10-13 External Clock Operation Timing Requirements1
1. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
fosc
0—
120
MHz
Clock Pulse Width3
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
tPW
3.0
ns
External clock input rise time4
4. External clock input rise time is measured from 10% to 90%.
trise
10
ns
External clock input fall time5
5. External clock input fall time is measured from 90% to 10%.
tfall
10
ns
Table 10-14 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8MHz input crystal.
fosc
48
8.4
MHz
PLL output frequency2 (fOUT)
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
fop
160
260
MHz
PLL stabilization time3 -40
° to +125°C
tplls
—1
10
ms
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10%
tPW
tfall
trise
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