參數(shù)資料
型號： MC56F8323MFBE
廠商： Freescale Semiconductor
文件頁數(shù)： 55/140頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 60MHZ 64-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，SCI，SPI
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 27
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 12K x 8
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
21
Preliminary
TMS
54
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
55
Schmitt
Input
Input,
pulled high
internally
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
TDO
56
Output
In reset,
output is
disabled,
pull-up is
enabled
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
TRST
58
Schmitt
Input
Input,
pulled high
internally
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware
device reset is required and the EOnCE/JTAG module must not be
reset. In this case, assert RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note:
For normal operation, connect TRST directly to VSS. If the design
is to be used in a debugging environment, TRST may be tied to VSS through
a 1K resistor.
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
52
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is PHASEA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
相關(guān)PDF資料
PDF描述
VJ2225Y474JBCAT4X CAP CER 0.47UF 200V 5% X7R 2225
MC56F8322MFAE IC DSP 16BIT 60MHZ 48-LQFP
MC56F8146VFVE IC DSP 16BIT 40MHZ 144-LQFP
HCZ472MBCDJ0KR CAP CER 4700PF 3KV 20% RADIAL
VJ1812Y125JBAAT4X CAP CER 1.2UF 50V 5% X7R 1812
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8323VFB60 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8323VFBE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8335 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller
MC56F8335E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller
MC56F8335MFG60 制造商:Freescale Semiconductor 功能描述:16 BIT HYBRID CONTROLLER - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*