56F8323 Technical Data, Rev. 17
70
Freescale Semiconductor
Preliminary
5.6.7
Interrupt Priority Register 6 (IPR6)
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Reserved—Bits 13–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.3
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ
IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TMRC0 IPL
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
Write
RESET
00000
0000000
0000
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