參數(shù)資料
型號(hào): MC56F8247MLH
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 69/88頁(yè)
文件大?。?/td> 0K
描述: DSC 48K FLASH 60MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲(chǔ)器容量: 48KB(24K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 管件
Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
71
7.27
5-Bit
Digital-to-Analog Converter (DAC) Parameters
7.28
HSCMP Specifications
7.29
Optimize Power Consumption
See Section 7.7, “Supply Current Characteristics,” for a list of IDD requirements for the MC56F825x/MC56F824x. This section
provides additional details for optimizing power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static] component, consists of the DC bias currents for the oscillator, leakage currents, PLL, and voltage
references. These sources operate independently of processor state or operating frequency.
1 No guaranteed specification within 5% of VDDA or VSSA
2 LSB = 0.806 mV
Table 43. 5-Bit DAC Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Reference Inputs
Vin
VDDA
VDDA
mV
Setup Delay
tPRGST
TBD
ns
Step size
VSTEP
3Vin/128
Vin/32
5Vin/128
V
Output Range
VDACOUT
Vin/32
Vin
ns
Table 44. HSCMP Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Analog input voltage
VAIN
VSSA – 0.01
VDDA + 0.01
V
Analog input offset voltage1
1 Offset when the degree of hysteresis is set to its minimum value.
VAIO
——
40
mV
Analog comparator hysteresis2
2 The range of hysteresis is based on simulation only. This range varies from part to part.
VH
1 to 16
mV
Propagation Delay, high speed mode (EN=1,
PMODE=1),
tDHSN
3
3 Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. V
DDA >
VLVI_WARNING => LVI_WARNING NOT ASSERTED.
70
140
ns
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0),
tAINIT
4
4 Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. V
DDA >
VLVI_WARNING => LVI_WARNING NOT ASSERTED.
400
600
ns
Total power =
A:
internal [static] component
+B: internal [state-dependent] component
+C: internal [dynamic] component
+D: external [dynamic] component
+E: external [static] component
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