參數(shù)資料
型號: MC56F8247MLH
廠商: Freescale Semiconductor
文件頁數(shù): 54/88頁
文件大?。?/td> 0K
描述: DSC 48K FLASH 60MHZ 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 48KB(24K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
58
Figure 17. External Clock Timing
7.14
Phase Locked Loop Timing
External clock input rise time4
trise
——
3
ns
External clock input fall time5
tfall
——
3
ns
Input high voltage overdrive by an external clock
Vih
0.85VDD
——
V
Input high voltage overdrive by an external clock
Vil
——
0.3VDD
V
1 Parameters listed are guaranteed by design.
2 See Figure 17 for details on using the recommended connection of an external clock driver.
3 The chip may not function if the high or low pulse width is smaller than 6.25 ns.
4 External clock input rise time is measured from 10% to 90%.
5 External clock input fall time is measured from 90% to 10%.
Table 30. Phase Locked Loop Timing
Characteristic
Symbol
Min
Typ
Max
Unit
PLL input reference frequency1
1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
fref
48
8
MHz
PLL output frequency2
2 The core system clock operates at 1/6 of the PLL output frequency.
fop
120
240
MHz
PLL lock time3 4
3 This is the time required after the PLL is enabled to ensure reliable operation.
4 From powerdown to powerup state at 60 MHz system clock state.
tplls
—40
100
s
Accumulated jitter using an 8 MHz external crystal as the PLL source5
5 This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 60 MHz system clock
frequency and using an 8 MHz oscillator frequency.
JA
——
TBD
%
Cycle-to-cycle jitter
tjitterpll
—350
ps
Table 29. External Clock Operation Timing Requirements1 (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
90%
50%
10%
90%
50%
10%
External
Clock
tPW
tfall
trise
VIL
VIH
Note: The midpoint is VIL + (VIH – VIL)/2.
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