參數(shù)資料
型號: MC56F8156VFVE
廠商: Freescale Semiconductor
文件頁數(shù): 55/178頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 144-LQFP
標準包裝: 60
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
56F8356 Technical Data, Rev. 13
148
Freescale Semiconductor
Preliminary
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL
clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL.
DCAOE and DCAEO are used to make this duty cycle adjustment where needed.
DCAOE and DCAEO are calculated as follows:
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
Figure 10-4 External Memory Interface Timing
DCAOE =
=
0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to
÷ 1
0.0 all other cases
DCAEO =
=
MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to
÷ 1
0.0 all other cases
Example of DCAOE and DCAEO calculation
Assuming prescaler is set for
÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high:
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
tDRD
tRDD
tAD
tDOH
tDOS
tDWR
tRDWR
tWAC
tWRRD
tWR
tAWR
tWRWR
tARDD
tRDA
tRDRD
tRD
tARDA
Data Out
Data In
A0-Axx,CS
RD
WR
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
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