參數(shù)資料
型號： MC56F8146VFVE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝： ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 99/178頁
文件大小： 880K
代理商： MC56F8146VFVE
Signal Pins
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
27
Preliminary
DS
(CS1)
(GPIOD9)
47
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Memory Select — This signal is actually CS1 in the EMI,
which is programmed at reset for compatibility with the 56F80x DS
signal. DS is asserted low for external data memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), DS is tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the 56F80x
devices.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
GPIOD0
(CS2)
48
Input/
Output
Input,
pull-up
enabled
Port D GPIO — These two GPIO pins can be individually
programmed as input or output pins.
Chip Select — CS2 - CS3 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS2 - CS3 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
GPIOD1
(CS3)
49
TXD0
(GPIOE0)
4
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
相關(guān)PDF資料
PDF描述
MC56F8146VFV 16-BIT, 120 MHz, OTHER DSP, PQFP144
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MC56F8367VVF 16-BIT, 120 MHz, OTHER DSP, PBGA160
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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