參數資料
型號: MC56F8146VFVE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: ROHS COMPLIANT, LQFP-144
文件頁數: 94/178頁
文件大小: 880K
代理商: MC56F8146VFVE
56F8346 Technical Data, Rev. 15
22
Freescale Semiconductor
Preliminary
CLKO
3
Output
In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test purposes.
See Part 6.5.7 for details.
A0
(GPIOA8)
138
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0 - A5 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A1
(GPIOA9)
10
A2
(GPIOA10)
11
A3
(GPIOA11)
12
A4
(GPIOA12)
13
A5
(GPIOA13)
14
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
相關PDF資料
PDF描述
MC56F8146VFV 16-BIT, 120 MHz, OTHER DSP, PQFP144
MC56F8167VPYE 16-BIT, 120 MHz, OTHER DSP, PQFP160
MC56F8367VVFE 16-BIT, 120 MHz, OTHER DSP, PBGA160
MC56F8367VVF 16-BIT, 120 MHz, OTHER DSP, PBGA160
MC56F8367MPYE 16-BIT, 120 MHz, OTHER DSP, PQFP160
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