參數(shù)資料
型號: MC56F8146VFV
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 56/178頁
文件大?。?/td> 880K
代理商: MC56F8146VFV
External Memory Interface Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
149
Preliminary
Table 10-16 External Memory Interface Timing
Characteristic
Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
Address Valid to WR Asserted
tAWR
WWS=0
-2.121
0.50
WWSS
ns
WWS>0
-1.805
0.75 + DCAOE
WR Width Asserted to WR Deasserted
tWR
WWS=0
-0.063
0.25 + DCAOE
WWS
ns
WWS>0
-0.253
0
Data Out Valid to WR Asserted
tDWR
WWS=0
-10.252
0.25 + DCAEO
WWSS
ns
WWS=0
-2.868
0.00
WWS>0
-9.505
0.50
WWS>0
-2.552
0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
tDOH
-1.512
0.25 + DCAEO
WWSH
ns
Valid Data Out Set-Up Time to WR
Deasserted
tDOS
-2.047
0.25 + DCAOE
WWS, WWSS
ns
-9.000
0.50
Valid Address after WR Deasserted
tWAC
-3.888
0.25 + DCAEO
WWSH
ns
RD Deasserted to Address Invalid
tRDA
-2.922
0.00
RWSH
ns
Address Valid to RD Deasserted
tARDD
-1.645
1.00
RWSS, RWS
ns
Valid Input Data Hold after RD Deasserted
tDRD
0.00
N/A1
1. N/A, since device captures data before it deasserts RD
ns
RD Assertion Width
tRD
0.257
1.00
RWS
ns
Address Valid to Input Data Valid
tAD
-14.414
1.00
RWSS, RWS
ns
-19.299
1.25 + DCAOE
Address Valid to RD Asserted
tARDA
-2.002
0.00
RWSS
ns
RD Asserted to Input Data Valid
tRDD
-12.411
1.00
RWSS, RWS
ns
-17.297
1.25 + DCAOE
WR Deasserted to RD Asserted
tWRRD
-1.323
0.25 + DCAEO WWSH, RWSS
ns
RD Deasserted to RD Asserted
tRDRD
-0.3572
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
0.00
RWSS, RWSH
MDAR3, 4
ns
WR Deasserted to WR Asserted
tWRWR
WWS=0
-1.442
0.75 + DCAEO
WWSS,
WWSH
ns
WWS>0
-0.695
1.00
RD Deasserted to WR Asserted
tRDWR
WWS=0
-0.476
0.50
RWSH,
WWSS,
MDAR3
ns
WWS>0
-0.160
0.75 + DCAOE
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