參數(shù)資料
型號: MC56F8145VFGE
廠商: Freescale Semiconductor
文件頁數(shù): 88/172頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 128-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8345 Technical Data, Rev. 17
22
Freescale Semiconductor
Preliminary
CLKO
6
Output
In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock
and postscaler clock. Other signals are also available for test
purposes.
See Part 6.5.7 for details.
A8
(GPIOA0)
15
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A8 - A13 specify six of the address lines for
external program or data memory accesses. Depending upon
the state of the DRV bit in the EMI bus control register (BCR), A8
- A13 and EMI control signals are tri-stated when the external
bus is inactive.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to address bus functionality and
must be programmed as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
A9
(GPIOA1)
16
A10
(GPIOA2)
17
A11
(GPIOA3)
18
A12
(GPIOA4)
19
A13
(GPIOA5)
20
GPIOB0
(A16)
27
Schmitt
Input/
Output
Input,
pull-up
enabled
Port B GPIO — These four GPIO pins can be individually
programmed as an input or output pin.
Address Bus — A16 - A19 specify four of the address lines for
external program or data memory accesses. Depending upon
the state of the DRV bit in the EMI bus control register (BCR),
A16 - A19 and EMI control signals are tri-stated when the
external bus is inactive.
After reset, the default state is GPIO.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.
GPIOB1
(A17)
28
GPIOB2
(A18)
29
GPIOB3
(A19)
30
Table 2-2 Signal and Package Information for the 128-Pin LQFP
Signal
Name
Pin No.
Type
State
During
Reset
Signal Description
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