參數(shù)資料
型號: MC56F8145VFG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: PLASTIC, LQFP-128
文件頁數(shù): 14/172頁
文件大?。?/td> 871K
代理商: MC56F8145VFG
56F8345 Technical Data, Rev. 17
110
Freescale Semiconductor
Preliminary
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
Write
RESET
0
1
111
1
010
0
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
1
Write
RESET
0
1
0
000
1
110
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
PWMB
PWMA0
0
CTRL
0
JTAG
0
Write
RESET
00
0
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