參數(shù)資料
型號: MC56F8123VFBE
廠商: Freescale Semiconductor
文件頁數(shù): 67/140頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: SCI,SPI
外圍設備: POR,WDT
輸入/輸出數(shù): 27
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8323 Technical Data, Rev. 17
32
Freescale Semiconductor
Preliminary
to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit
added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the
desired frequency accuracy is achieved.
The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash
information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the
boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information,
see the 56F8300 Peripherals User Manual.
3.4 Internal Clock Operation
At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock
reference for the PLL. Software should power down the block not being used and program the PLL for the
correct frequency.
Figure 3-4 Internal Clock Operation
Crystal
OSC
Relaxation
OSC
CLK_MODE
XTAL
EXTAL
MUX
PRECS
PLLCID
PLL
x (1 to 128)
Postscaler
÷ (1, 2, 4, 8)
÷ 2
Prescaler
÷ (1, 2, 4, 8)
Lock
Detector
Loss of
Reference
Clock
Detector
MU
X
SYS_CLK2
source to
the SIM
Postscaler CLK
PLLDB
PLLCOD
LCK
Bus Interface
& Control
Bus
Interface
FREF
FEEDB
A
CK
loss of reference
clock interrupt
MSTR_OSC
FOUT
FOUT/2
ZSRC
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