參數(shù)資料
型號(hào): MC56F8123VFBE
廠商: Freescale Semiconductor
文件頁數(shù): 49/140頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 27
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8323 Technical Data, Rev. 17
16
Freescale Semiconductor
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as
detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row
describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8323
56F8123
Power (VDD or VDDA)6
6
Power Option Control
1
Ground (VSS or VSSA)5
5
Supply Capacitors1 & VPP
2
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs
2. The VPP input shares the IRQA input
44
PLL and Clock
2
Interrupt and Program Control
2
Pulse Width Modulator (PWM) Ports3
3. Pins in this section can function as SPI #1 and GPIO
12
Serial Peripheral Interface (SPI) Port 04
4. Pins in this section can function as SCI #1 and GPIO
48
Quadrature Decoder Port 05
5. Alternately, can function as Quad Timer A pins or GPIO
4—
CAN Ports
2
Analog-to-Digital Converter (ADC) Ports
13
Timer Module Port C6
6. Two pins can function as SCI #0 and GPIO
Note: See Table 1-1 for 56F8123 functional differences.
33
Timer Module Port A
4
JTAG/Enhanced On-Chip Emulation (EOnCE)
5
Temperature Sensse
1
Dedicated GPIO
10
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