參數(shù)資料
型號： MC56F8011VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 82/126頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 32-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 12KB（6K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
Register Descriptions
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
59
5.5.8
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.5.8.1
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.9
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.5.9.1
Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.9.2
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.10
Fast Interrupt 1 Match Register (FIM1)
Figure 5-12 Fast Interrupt 1 Match Register (FIM1)
5.5.10.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.10.2
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET
00000
0000000
0000
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
00000
0000000
0000
Base + $9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1
Write
RESET
00000
0000000
0000
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