- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄10990 > MC56F8011VFAE (Freescale Semiconductor)IC DIGITAL SIGNAL CTLR 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MC56F8011VFAE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 104/126頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL SIGNAL CTLR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 12KB（6K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤(pán) |
| 配用： | CPA56F8013-ND - BOARD SOCKET FOR MC56F8013 APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)當(dāng)前第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)
Clock Generation Overview
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
79
Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.10.3
Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.4 Clock Generation Overview
The SIM uses master clocks, 2X system clock at a maximum of 64MHz, from the OCCS module to
produce the peripheral and system (core and memory) clocks at a maximum of 32MHz. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. The high speed
peripheral clock from OCCS operates at three times the system clock for PWM and Quad Timer module
at a maximum of 96MHz.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). The
relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz), or powered down. An
8MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide a variety of high speed
clock rates. Either the postscaled PLL output or input clock of PLL signal can be selected to produce the
master clocks to the SIM. When the PLL is not selected, the high speed peripheral clock is disabled and
the 2X system clock is input clock from either internal relaxation oscillator or external clock source.
In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral
User Manual for further details.
6.5 Power-Down Modes
The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
ISAL[21:6]
Write
RESET
11111
1
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Core and memory
clocks disabled
Peripheral clocks
enabled
Device is fully functional
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S9S08DN32F1MLC | IC MCU 8BIT 32KB FLASH 32LQFP |
| MC9S08MM32VLH | IC MCU 8BIT 32K FLASH 64LQFP |
| MC9S08JE128CMB | IC MCU 8BIT 128K FLASH 81MAPBGA |
| MC9S08AW60VFGE | IC MCU 8BIT 60KB FLASH 44-LQFP |
| MC9S08DN32AVLF | MCU 8BIT 32K FLASH 48-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8013 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013E | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013MFAE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16Bit DSPHC ANGUILLA RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8013MFAER2 | 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC ANGUILLA - Tape and Reel |
| MC56F8013PB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。