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參數(shù)資料
| 型號： | MC54HC595 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs |
| 中文描述： | 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊態(tài)輸出 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 297K |
| 代理商： | MC54HC595 |
MC54/74HC595A
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8–bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low– to–high transition on this
input causes the data at the Serial Input pin to be shifted into
the 8–bit shift register.
Reset (Pin 10)
Active–low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8–bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low–to–high transition on this
input latches the shift register data.
Output Enable (Pin 13)
Active–low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA–QH) into the high–
impedance state. The serial output is not affected by this
control unit.
OUTPUTS
QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3–state, latch outputs.
SQH (Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8–bit shift register. This output does not
have three–state capability.
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| MC54HC595AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs |
| MC54HC597AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch |
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