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參數(shù)資料
| 型號： | MC54-74HC393A |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Stage Binary Ripple Counter |
| 中文描述： | 雙4位的二進制紋波計數(shù)器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 240K |
| 代理商： | MC54-74HC393A |
MC54/74HC393A
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flip–flops are toggled and the
counter state advances on high–to–low transitions of the
clock input.
CONTROL INPUTS
Reset (Pins 2, 12)
Active–high, asynchronous reset. A separate reset is pro-
vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
SWITCHING WAVEFORMS
tPHL
VCC
GND
VCC
GND
50%
50%
50%
trec
CLOCK
Q
RESET
Figure 1.
Figure 2.
Figure 3. Test Circuit
Q1
Q2
Q3
Q4
CLOCK
RESET
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
EXPANDED LOGIC DIAGRAM
* Includes all probe and jig capacitance
CL*
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
CLOCK
Q
90%
50%
10%
tf
tr
VCC
GND
tw
1/fmax
tPLH
tPHL
90%
50%
10%
tTLH
tTHL
C
D
Q
tw
Q
C
D
Q
Q
C
D
Q
Q
C
D
Q
Q
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