
Chapter 3 Module Mapping Control (MMCV4) Block Description
124
MC9S12Q128
Freescale Semiconductor
Rev 1.10
unimplemented locations within the register space or to locations that are removed from the map (i.e., ports
A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this
pin is used for general purpose I/O.
3.4.3
Memory Expansion
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
in the physical memory space. The paged memory space can consist of solely on-chip memory or a
combination of on-chip and off-chip memory. This partitioning is congured at system integration through
the use of the paging conguration switches (pag_sw1:pag_sw0) at the core boundary. The options
available to the integrator are as given in
Table 3-16 (this table matches
Table 3-12 but is repeated here for
easy reference).
Based upon the system conguration, the program page window will consider its access to be either
NOTE
The partitioning as dened in
Table 3-17 applies only to the allocated
memory space and the actual on-chip memory sizes implemented in the
system may differ. Please refer to the device overview chapter for actual
sizes.
Table 3-16. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0
Off-Chip Space
On-Chip Space
00
876K bytes
128K bytes
01
768K bytes
256K bytes
10
512K bytes
11
0K byte
1M byte
Table 3-17. External/Internal Page Window Access
pag_sw1:pag_sw0
Partitioning
PIX5:0 Value
Page Window
Access
00
876K off-Chip,
128K on-Chip
0x0000–0x0037
External
0x0038–0x003F
Internal
01
768K off-chip,
256K on-chip
0x0000–0x002F
External
0x0030–0x003F
Internal
10
512K off-chip,
512K on-chip
0x0000–0x001F
External
0x0020–0x003F
Internal
11
0K off-chip,
1M on-chip
N/A
External
0x0000–0x003F
Internal