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參數(shù)資料
| 型號(hào)： | MC33990DR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCEIVER J-1850 BUS 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 電源電壓： | 9 V ~ 16 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC33990DR2CT |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33990
TYPICAL APPLICATIONS
FUNCTIONAL PIN DESCRIPTION
transition before 96
μs, one logic state is inferred. If there is a
bus transition after 96
μs, the other logic state is inferred. The
“end of data” bit is a logic [0] and lasts 200
μs. If there is no
activity on the bus for 280
μs to 320 μs following a broadcast
message, multiple unit nodes may arbitrate for control of the
next message. During an arbitration, after the “start of frame”
bit has been transmitted, the secondary node transmitting the
most consecutive logic [0] bits will be granted sole
transmission access to the bus for that message.
Loss of Assembly Ground Connection
The definition of a loss of assembly ground condition at the
device level is that all pins of the 33990, with the exception of
BUS and LOAD, see a very low impedance to VBAT.
The LOAD pin of the device has an internal transistor
switch connected to it that is normally saturated to ground.
This pulls the LOAD-side of the external resistor (tied from
BUS to LOAD) to ground under normal conditions. The LOAD
pin switch is essentially that of an “upside down” FET, which
is normally biased “on” so long as module ground is present
and biased “off” when loss-of-ground occurs. When a loss of
assembly ground occurs, the load transistor switch is self-
biased “off”, allowing no more than 100
μA of leakage current
to flow in the LOAD pin. During such a loss of assembly
ground condition, the BUS and LOAD pins exhibit a high
impedance to VBAT; all other pins will exhibit a low impedance
to VBAT. During this condition the BUS pin is prevented from
sourcing any current or loading the bus, which would cause a
corruption of any data being transmitted on the bus. While a
particular assembly is experiencing a loss of ground, all other
assembly nodes are permitted to function normally. It should
be noted that with other nodes existing on the bus, the bus
will always have some minimum/maximum impedance to
Loss of Assembly Battery Connection
The definition of a loss of assembly battery condition at the
device level is that the VBAT pin of the 33990 sees an infinite
impedance to VBAT, but there is some undefined impedance
between these pins and ground.
Figure 14. Typical Application
BUS
+VBAT
SLEEP
TX
RX
4X/LOOP
GND
LOAD
Primary
Node
MCU
VBAT
Secondary
Nodes
33990
10.6
k
Ω
470pF
47
μH
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