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參數(shù)資料
| 型號： | MC33976 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Dual Gauge Driver with Configurable Response Time(帶可設(shè)置響應(yīng)時間的雙標(biāo)尺驅(qū)動器) |
| 中文描述： | 雙計驅(qū)動器，可配置的響應(yīng)時間（帶可設(shè)置響應(yīng)時間的雙標(biāo)尺驅(qū)動器） |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 5332K |
| 代理商： | MC33976 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
20
33976
FUNCTIONAL DEVICE OPERATION
COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS
The value of RS also determines the last velocity position
step for which the Hold Counts are applied:
Last Velocity Position w/ Hold Counts = RS + 2
The number of hold counts per applicable velocity step is
determined by the value written to HC3:HC0 (HC) and can
range from 0 to 15 steps. This number of hold counts will be
applied to each step below the Hold Count Cut-In as
determined by HCP and RS. The default value of HC is 5.
Note: the following relationship between the variables
must be adhered to for the state machine to work properly:
HC x (HCP x 8 - 1) + (225 - RS) < 512
Therefore, if RS = 0 and the Hold Count Cut-In point is 64,
the largest value of Hold Counts you can choose is 4.
4 * (64 - 1) + (225 - 0) = 477
The GSEL bit determines which of the two gauges the rest
of the RMPSELR bits are applied to. A GSEL bit set to logic
1 will apply the RMPSELR data to Gauge 1 and, Logic 0 to
Gauge 0, respectively. Configuring both gauges requires two
writes to this register.
The bits in
Table 15
are
write-only
.
GSEL 12 (D12) — Gauge Select bit. The value of this bit
determines the gauge for which the settings apply (refer to
page
17
):
1 = Gauge 1
0 = Gauge 0
GSEL 11 (D11) — This bit must be transmitted as Logic 0
for valid commands.
HCP2 : HPC0 (D10 D8) — Hold Count Cut-in Point
variable. These bits determine HCP, which is then multiplied
by 8, and added to the RS number, to determine the actual
Hold Count Cut-In Step value. The values of HCP range from
1 to 8 as shown in
Table 16
. The default value is 2.
.
Table 16. First Hold Count Velocity Position
HC3 : HC0 (D7 : D4) — These bits determine the number of
Hold Counts that will be applied to the steps that are
determined by the HCP2:HCP0 and RS3:RS0 bits. The HC
values range from 0 to 15 and are shown in
Table 17
. The
default value is 5.
RS3 : RS0 (D3 D0) — These bits determine the number of
velocity steps that are truncated from the Velocity Position
ramp. The values range from 0 to 15 and are shown in
Table 18
. The default value is 0.
Table 15. Ramp Selection Register (RMPSELR)
Address 101
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
–
–
–
–
–
–
–
–
–
–
–
–
–
Write
GSEL 12 GSEL 11
HCP2
HCP1
HCP0
HC3
HC2
HC1
HC0
RS3
RS2
RS1
RS0
HCP2
HCP1
HCP0
Velocity Step
(HCP x 8 + RS)
0
0
0
64 + RS
0
0
1
8 + RS
0
1
0
16 + RS
0
1
1
24 + RS
1
0
0
32 + RS
1
0
1
40 + RS
1
1
0
48 + RS
1
1
1
56 + RS
Table 17. Hold Counts Per Step
HC3
HC2
HC1
HC0
Hold Counts /
Step (HC)
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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