參數(shù)資料
型號(hào)： MC33888FB
廠商： MOTOROLA INC
元件分類： 外設(shè)及接口
英文描述： Quad High-Side and Octal Low-Side Switch for Automotive
中文描述： 40 A BUF OR INV BASED PRPHL DRVR, PQFP64
封裝： 0.65 MM PITCH, MO-188, POWER PACK-64
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 667K
代理商： MC33888FB
33888
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Address 110—Watchdog and Current Sense Configuration
Register (WDCSCR)
The WDCSCR register is used by the MCU to configure the
watchdog timeout and the CSNS0-1 and CSNS2-3 terminals.
The watchdog timeout is configured using bits D4 and D5. The
state of D4 and D5 determine the divided value of the WDTO.
For example, if D5 and D4 are logic [0] and logic [0],
respectively, then the WDTO will be in the default state as
specified in
Table 3
, page 21. A D5 and a D4 of logic [0] and
logic [1] will result in a watchdog timeout of WDTO
÷
2.
Similarly, a D5 and a D4 of logic [1] and logic [0] result in a
watchdog timeout of WDTO
÷
4, and a D5 and a D4 of logic [1]
and logic [1] result in a watchdog timeout of WDTO
÷
8. Note
that when D5 and D4 bits are programmed for the desired
watchdog timeout period, the WD bit (D15) should be toggled
as well to ensure that the new timeout period is programmed at
the beginning of a new count sequence.
CSNS0-1 is the current sense output for the HS0 and HS1
outputs. Similarly, the CSNS2-3 terminal is the current sense
output for the HS2 and HS3 outputs. In this mode, a logic [1] on
any or all of the message bits that control the high-side outputs
will result in the sensed current from the corresponding output
being directed out of the appropriate CSNS output. For
example, if D1 and D0 are both logic [1], then the sensed
current from HS0 and HS1 will be summed into the CSNS0-1.
If D2 is logic [1] and D3 is logic [0], then only the sensed current
from HS2 will be directed out of CSNS2-3.
Address 001—Open Load Configuration Register (OLCR)
The OLCR register allows the MCU to configure each of the
outputs for open load fault detection. While in this mode, a
logic [1] on any of the D3:D0 message bits will disable the
corresponding outputs’ circuitry that allows the device to detect
open load faults while the output is OFF. For the low-side
drivers, a logic [1] on any of the D11:D4 bits will enable the
open load detection circuitry. This feature allows the MCU to
minimize load current in some applications and may be useful
to diagnose output shorts to battery (for HS).
Address 101—Current Limit Overcurrent Configuration
Register (CLOCCR)
The CLOCCR register allows the MCU to individually
override the peak current limit levels for each of the high-side
outputs. A logic [1] on any or all of the D3:D0 bit(s) results in the
corresponding HS3:HS0 output terminals to current limit at the
sustain current limit level. This register also allows the MCU to
enable or disable the overcurrent shutdown of the low-side
output terminals. A logic [1] on any or all of the D11:D4
message bit(s) will result in the corresponding LS11:LS4
terminals latching off if the current exceeds I
LIM
after a timeout
of t
DLY(
FS
)
.
Address 011—Not Used
Not currently used.
Address 111—TEST
The TEST register is reserved for test and is not accessible
via SPI during normal operation.
Serial Output Communication (Devise Status
Return Data)
When the
CS
terminal is pulled low, the output status register
for each output is loaded into the output register and the fault
data is clocked out MSB (OD15) first as the new message data
is clocked into the SI terminal.
OD15 reflects the state of the watchdog bit (D15) that was
addressed during the prior SOCR communication (refer to
Table 4
, page 23). If bit OD15 is logic [0], then the three MSBs
OD14:OD12 will reflect the logic states of the IHS0, IHS1, and
FSI terminals, respectively. If bit OD15 is logic [1], then the
same three MSB bits will reflect the logic states of the IHS2,
IHS3, and WAKE terminals. The next twelve bits clocked out of
SO following a low transition of the
CS
terminal (OD11:OD0)
will reflect the state of each output, with a logic [1] in any of the
bits indicating that the respective output experienced a fault
condition prior to the
CS
transition. Any bits clocked out of the
SO terminal after the first 16 will be representative of the initial
message bits that were clocked into the SI terminal since the
CS
terminal first transitioned to a logic [0]. This feature is useful for
daisy chaining devices as well as message verification.
Following a
CS
transition logic [0] to logic [1], the device
determines if the message was of a valid length (a valid
message length is one that is a multiple of 16 bits) and if so,
latches the data into the appropriate registers. At this time, the
SO terminal is tri-stated and the fault status register is now able
to accept new fault status information.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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MC33888FBR2 功能描述:電源開(kāi)關(guān) IC - 配電 QHSOLSS RoHS:否 制造商:Exar 輸出端數(shù)量:1 開(kāi)啟電阻（最大值）:85 mOhms 開(kāi)啟時(shí)間（最大值）:400 us 關(guān)閉時(shí)間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5
MC33888PNB 制造商:FREESCALE-SEMI 功能描述:
MC33888PNBR2 制造商:FREESCALE-SEMI 功能描述:
MC33889BDW 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC LIGHT PASS 3.3 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
MC33889BDWR2 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC LIGHT PASS 3.3 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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