參數資料
型號: MC33888
廠商: Motorola, Inc.
英文描述: Quad High-Side and Octal Low-Side Switch for Automotive
中文描述: 四高邊和八路低端汽車開關
文件頁數: 23/32頁
文件大?。?/td> 667K
代理商: MC33888
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33888
23
MODES OF OPERATION
Watchdog and Fail-Safe Operation
The watchdog is enabled and a timeout is started when the
WAKE or
RST
transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to V
PWR
with a series limiting
resistance that limits the internal clamp current. The timeout is
a multiple of an internal oscillator. As long as the WDIN terminal
or the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog timeout, WDTO (or a divided
value configured during a WDCSCR message), then the device
will operate normally. If the watchdog timeout occurs before the
WD bit or the WDIN terminal is toggled, then the device will
revert to a Fail-Safe mode until the device is reinitialized (if the
FSI terminal is left disconnected).
During Fail-Safe mode, all outputs will be OFF except for
HS0 and HS2, which will be driven ON regardless of the state
of the various direct inputs and modes (
Table 5
). The device
can be brought out of the Fail-Safe mode by transitioning the
WAKE and
RST
terminals from logic [1] to logic [0]. In the event
the WAKE terminal was not transitioned to a logic [1] during
normal operation and the watchdog times out, then the device
can be brought out of fail-safe by bringing the
RST
to a logic [0].
If the FSI terminal is tied to GND, then the watchdog, and
therefore fail-safe operation, will be disabled.
Table 4. Serial Output Bit Assignment
Bit Sig
SO
Msg Bit
Message Bit Description
MSB
OD15
Reflects the state of the Watchdog bit from the
previously clocked-in message.
OD14
If OD15 is logic [0], then this bit will reflect the state
of the direct input IHS0. If OD15 is logic [1], then this
bit will reflect the state of IHS2.
OD13
If OD15 is logic [0], then this bit will reflect the state
of the direct input IHS1. If OD15 is logic [1], then this
bit will reflect the state of IHS3.
OD12
If OD15 is logic [0], then this bit will reflect the state
of the input FSI. If OD15 is logic [1], then this bit will
reflect the state of the input WAKE.
OD11
Reports the absence or presence of a fault on LS11.
OD10
Reports the absence or presence of a fault on LS10.
Bit Sig
SO
Msg Bit
Message Bit Description
OD9
Reports the absence or presence of a fault on LS9.
OD8
Reports the absence or presence of a fault on LS8.
OD7
Reports the absence or presence of a fault on LS7.
OD6
Reports the absence or presence of a fault on LS6.
OD5
Reports the absence or presence of a fault on LS5.
OD4
Reports the absence or presence of a fault on LS4.
OD3
Reports the absence or presence of a fault on HS3.
OD2
Reports the absence or presence of a fault on HS2.
OD1
Reports the absence or presence of a fault on HS1.
LSB
OD0
Reports the absence or presence of a fault on HS0.
Table 4. Serial Output Bit Assignment (continued)
Table 5. Fail-Safe Operation and Transitions
to Other 33888 Modes
WAKE RST WDTO HS0 HS2
LS[4:11],
HS[1,3]
Comments
0
0
x
OFF OFF
OFF
Device in Sleep mode.
1
0
NO
OFF OFF
OFF
All outputs are OFF.
When
RST
transitions
to logic [1], device is in
default.
1
0
YES
ON
ON
OFF
Fail-Safe mode.
Device reset into
Default mode by
transitioning WAKE to
logic [0].
0
1
NO
S
S
S
Device in Normal
operating mode.
0
1
YES
ON
ON
OFF
Fail-Safe mode.
Device reset into
Default mode by
transitioning
RST
to
logic [0].
1
1
NO
S
S
S
Device in Normal
operating mode.
1
1
YES
ON
ON
OFF
Fail-Safe mode.
Device reset into
Default mode by
transitioning
RST
and
WAKE to logic [0].
Assumptions: Normal operating voltage and junction temperatures,
FSI terminal floating.
x=Don’t care.
S=State determined by SPI and/or direct input configurations.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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