
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33886
 15
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Numerous protection and operational features (speed, 
torque, direction, dynamic braking, and PWM control), in 
addition to the 5.0 A current capability, make the 33886 a very 
attractive, cost-effective solution for controlling a broad range of 
fractional horsepower DC motors. A pair of 33886 devices can 
be used to control bipolar stepper motors in both directions. In 
addition, the 33886 can be used to control permanent magnet 
solenoids in a push-pull variable force fashion using PWM 
control. The 33886 can also be used to excite transformer 
primary windings with a switched square wave to produce 
secondary winding AC currents. 
As shown in 
Figure 1
, Simplified Internal Block Diagram, 
page 2, the 33886 is a fully protected monolithic H-Bridge with 
Fault Status reporting. For a DC motor to run the input 
conditions need be as follows: D1 input logic Low, D2 input logic 
High, FS flag cleared (logic High), with one IN logic Low and the 
other IN logic High to define output polarity. The 33886 can 
execute dynamic braking by simultaneously turning on either 
both high-side
MOSFETs or both low-side MOSFETs in the 
output H-Bridge; e.g., IN1 and IN2 logic High or IN1 and IN2 
logic Low.
The 33886 outputs are capable of providing a continuous DC 
load current of 5.0 A from a 40 V V+ source. An internal charge 
pump supports PWM frequencies up to 10 kHz. An external 
pull-up resistor is required for the open drain FS terminal for 
fault status reporting. 
Two independent inputs (IN1 and IN2) provide control of the 
two totem-pole half-bridge outputs. Two disable inputs (D1 and 
D2) are for forcing the H-Bridge outputs to a high impedance 
state (all H-Bridge switches OFF).
The 33886 has undervoltage shutdown with automatic 
recovery, active current limiting, output short-circuit latch-OFF, 
and overtemperature latch-OFF. An undervoltage shutdown, 
output short circuit latch-OFF, or overtemperature latch-OFF 
fault condition will cause the outputs to turn OFF (i.e., become 
high impedance or tri-stated) and the fault output flag to be set 
Low. Either of the Disable inputs or V+ must be “toggled” to 
clear the fault flag. 
The short circuit/overtemperature shutdown scheme is 
unique and best described as using a junction temperature-
dependent active current “fold back” protection scheme. When 
a short circuit condition is experienced, the current limited 
output is “ramped down” as the junction temperature increases 
above 160
°
C, until at 175
°
C the current has decreased to about 
2.5 A. Above 175
°
C, overtemperature shutdown (latch-OFF) 
occurs. This feature allows the device to remain in operation for 
a longer time with unexpected loads, while still retaining 
adequate protection for both the device and the load.
FUNCTIONAL TERMINAL DESCRIPTION
PGND and AGND
Power and analog ground terminals. The power and analog 
ground terminals should be connected together with a very low 
impedance connection.
V+
V+ terminals are the power supply inputs to the device. All V+ 
terminals must be connected together on the printed circuit 
board with as short as possible traces offering as low 
impedance as possible between terminals.
V+ terminals have an undervoltage threshold. If the supply 
voltage drops below a V+ undervoltage threshold, the output 
power stage switches to a tri-state condition and the fault status 
flag is set and the Fault Status terminal voltage switched to a 
logic Low. When the supply voltage returns to a level that is 
above the threshold, the power stage automatically
resumes 
normal operation according to the established condition of the 
input terminals and the fault status flag is automatically reset 
logic High. 
Fault Status (FS)
This terminal is the device fault status output. This output is 
an active Low open drain structure requiring a pull-up resistor to 
5.0 V. Refer to 
Table 1, Truth Table
, page 14.
IN1, IN2, D1, and D2
These terminals are input control terminals used to control 
the outputs. These terminals are 5.0 V CMOS-compatible 
inputs with hysteresis. The IN1 and IN2 independently control 
OUT1 and OUT2, respectively. D1 and D2 are complimentary 
inputs used to tri-state disable the H-Bridge outputs.
When either D1 or D2 is set (D1 = logic High or D2 = logic 
Low) in the disable state, outputs OUT1 and OUT2 are both tri-
state disabled; however, the rest of the device circuitry is fully 
operational and the supply I
Q(standby)
 current is reduced to a few 
milliamperes. Refer to 
Table 1, Truth Table
, 
and
STATIC 
ELECTRICAL CHARACTERISTICS
table, page 5.
F
Freescale Semiconductor, Inc.
  Go to: www.freescale.com
n
.