參數(shù)資料
型號: MC33884
廠商: Motorola, Inc.
英文描述: SWITCH MONITOR INTERFACE
中文描述: 開關(guān)監(jiān)視器接口
文件頁數(shù): 7/21頁
文件大小: 235K
代理商: MC33884
7
MOTOROLA TSG IC DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions of 4.75 V
VDD
5.25 V, 9.0 V
VPWR
16 V, –40
°
C
TC
105
°
C, unless otherwise noted. Typical values, where applicable, reflect the parameter’s approximate
average value with VPWR = 13 V, TA = 25
°
C.)
Characteristics
Symbol
Min
Typ
Max
Units
SWITCH INPUT
Pulse Wetting Current Duration
tpulse
tINT(delay)
30
34
43
ms
Interrupt Delay Time
2.5
13
ms
SCLK Frequency vs. SO Load Capacitance
200 pF
160 pF
120 pF
fSCLK
3.2
3.5
4.0
MHz
DIGITAL INTERFACE TIMING
Falling Edge of CSB to Rising Edge of SCLK (Note 1)
(Required Set–up Time)
tlead
100
140
ns
Falling Edge of SCLK to Rising Edge of CSB
(Required Set–up Time)
tlag
50
ns
SI to Rising Edge of SCLK (Required Set–up Time)
tSU2
tH2
tSU1
tH1
tr(SO)
tf(SO)
25
45
ns
Rising Edge of SCLK to SI (Required Hold Time)
25
45
ns
SO to Rising Edge of SCLK (Required Set–up Time)
90
125
ns
Rising Edge of SCLK to Falling Edge of SO (Hold Time)
90
125
ns
SO Rise Time, SO Fall Time (CL = 200 pF)
30
50
ns
SI, CSB, SCLK Incoming SIgnal Rise Time (Note 2)
tr(SI)
tf(SI)
tSO(en)
tSO(DIS)
tvalid
tREC
50
ns
SI, CSB, SCLK Incoming Signal Fall Time (Note 2)
50
ns
Time from Falling Edge of CSB to SO Low Impedance (Note 3)
80
110
ns
Time for Rising Edge of CSB to SO High Impedance (Note 4)
80
110
ns
Time from Falling Edge of SCLK to SO Data Valid (Note 5)
65
105
ns
Recovery Time for Sequential Transfers
100
120
ns
NOTES:
1. This parameter is guaranteed by design, but not production tested.
2. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
3. Time required for output status data to be available for use at SO pin.
4. Time required for output states data to be terminated at SO pin.
5. Time required to obtain valid data out from SO following the falling edge of SCLK.
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