參數(shù)資料
型號(hào)： MC33780EG
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 7/37頁(yè)
文件大?。?/td> 0K
描述： IC DBUS MASTER DUAL DIFF 16-SOIC
標(biāo)準(zhǔn)包裝： 47
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
PROTOCOL ENGINE
This block converts the data to be transmitted from the
registers into the DBUS sequences, and converts DBUS
response sequences to data in the registers. It generates the
proper DBUS timing.
The DBUS transmit protocol uses a return to 1 type data
with a duty cycle determined by the logic state. The protocol
requires Cyclical Redundancy Check (CRC) generation and
validation.
Figure 10. Driver/Receiver Block Diagram
DBUS DRIVER /RECEIVER (PHYSICAL LAYER)
This block translates the transmit data to the voltage and
current needed to drive the DBUS. It also detects the
response current from the slave devices and translates that
current into digital levels. These circuits can drive their
outputs to the levels listed in Table 5.
The internal signal DSIF controls the Idle to Signalling
state change, and internal signal DSIS controls the signal
level, high or low. DSIR is the slave device response signal to
the logic. This is shown in Table 6.
The DBUS driver block diagram is shown in Figure 10. The
circuit uses independent drivers for the Idle and Signal states.
This allows each driver to be optimized for its function. The
Idle driver is active in Idle and during the transitions from Idle
to Signal high and Signal high to Idle. The Signal driver is only
active during actual signaling. Both drivers are disabled in
HiZ.
The Idle driver is required to supply a high current to
recharge the Slave device storage capacitors. It is also
required to drive the DBUS load capacitances and control the
slew rate over a wide supply voltage range. The DnH and
DnL Idle drivers are each optimized for their specific drive
requirements.
The Signal driver is optimized for driving the DBUS load,
and has the requirement of good slew rate control and
stability over a wide range of load conditions. The DnH and
DnL outputs use identical Signal driver circuits.
To ensure stability of the Signal driver, capacitors must be
connected between each output and ground. These are the
DBUS common mode capacitors. In addition, a bypass
capacitor is required at VSUP. These capacitors must be
located close to the IC pins and provide a low impedance
path to ground.
DnH
DnL
Differential
Control
DSIR
DSIS
DSIF
Common
Overvoltage TLIM
Signal
Generation
Mode
Correction
Signal
Idle
Comp.
Table 6. Internal Signal Truth Table
DSIF
DSIS
TLIM
DSIR
DnD
0
Return Data
Signal Low
0
1
0
Return Data
Signal High
1
0
High Impedance
1
0
Idle
X
1
0
High Impedance
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