參數(shù)資料
型號(hào)： MC33742EPR2
廠商： Freescale Semiconductor
文件頁數(shù)： 34/71頁
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/CAN 48-QFN
標(biāo)準(zhǔn)包裝： 2,000
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN-EP（7x7）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
33742
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33742 28-Pin Connections
Table 2. 33742 28-Pin Definitions
A functional description of each pin can be found in the Functional Pin description section beginning on page 22.
Pin
Pin Name
Formal Name
Definition
1
RXD
Receive Data
CAN bus receive data output pin.
2
TXD
Transmit Data
CAN bus transmit data input pin.
3
VDD
Voltage Digital Drain
5.0 V regulator output pin. Supply pin for the MCU.
4
RST
Reset Output
(Active LOW)
This is the device reset output pin whose main function is to reset the MCU. This pin has
an internal
-up current source to VDD.
5
INT
Interrupt Output
(Active LOW)
This output is asserted LOW when an enabled interrupt condition occurs. The output is
a push-pull structure.
6–9
20–23
GND
Ground
These device ground pins are internally connected to the package lead frame to provide
a 33742-to-PCB thermal path.
10
V2
Voltage Source 2
Sense input for the V2 regulator using an external series pass transistor. V2 is also the
internal supply for the CAN transceiver.
11
V2CTRL
Voltage Source 2 Control
Output drive source for the V2 regulator connected to the external series pass transistor.
12
VSUP
Voltage Supply
Supply input pin for the 33742.
13
HS
High Side Output
Output of the internal high side switch. The output current is internally limited to 150 mA.
14–17
L0-L3
Level 0-3 Inputs
Inputs from external switches or from logic circuitry.
18
CANH
CAN High Output
CAN high output pin.
19
CANL
CAN Low Output
CAN low output pin.
24
SCLK
Serial Data Clock
Clock input pin for the Serial Peripheral Interface (SPI).
25
MISO
Master In Slave Out
SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-
impedance state.
26
MOSI
Master Out Slave In
SPI data received by the 33742.
27
CS
Chip Select
(Active LOW)
The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted
LOW, the 33742 is the selected device of the SPI bus.
28
WDOG
Watchdog Output
(Active LOW)
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
WDOG
MISO
SCLK
GND
CANL
CANH
L3
L2
L1
CS
MOSI
RXD
RST
INT
GND
V2
V2CTRL
VSUP
HS
L0
TXD
VDD
4
5
6
7
8
9
10
11
12
13
14
2
3
28
25
24
23
22
21
20
19
18
17
16
15
27
26
1
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