參數(shù)資料
型號(hào)： MC33742
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver(帶增強(qiáng)型高速CAN收發(fā)器的系統(tǒng)基片)
中文描述： 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器（帶增強(qiáng)型高速的CAN收發(fā)器的系統(tǒng)基片）
文件頁數(shù)： 42/52頁
文件大?。?/td> 1087K
代理商： MC33742
33742
42
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Wake-Up Register (WUR)
Tables 22
through
24
contain various Wake-Up Register
information. Local wake-up inputs L0:L3 can be used in both
Normal and Standby modes as port expander, as well as for
waking up the 33742 from Sleep or Stop modes (
Table 22
).
Wake-up inputs can be configured by pair. L0 and L1 can be
configured together, and L2 and L3 can be configured together
(
Table 23
).
——————————————————
Table 22. Wake-Up Register
WUR
R/W
D3
D2
D1
D0
$100b
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
Reset
Value
–
0
0
0
0
Reset
Condition
(Write)
(Note 58)
–
POR, NR2R, N2R, STB2R, STO2R
Notes
58.
See
Table 8
, page 38, for definitions of reset conditions.
Table 23. Wake-Up Register Control Bits
LCTR3 LCTR2 LCTR1 LCTR0
L0:L1 Config
L2:L3 Config
x
x
0
0
Inputs Disabled
–
x
x
0
1
High Level
Sensitive
x
x
1
0
Low Level
Sensitive
x
x
1
1
Both Level
Sensitive
0
0
x
x
–
Inputs Disabled
0
1
x
x
High Level
Sensitive
1
0
x
x
Low Level
Sensitive
1
1
x
x
Both Level
Sensitive
x = Don’t care.
Table 24. Wake-Up Register Status Bits
(Note 59)
Name
Value
Description
L3WU
0 or 1
If bit = 1, wake-up occurred from Sleep
or Stop modes; if bit = 0, no wake-up
has occurred.
When device is in Normal or Standby
mode, bit reports the State on Lx
terminal (LOW or HIGH) (0 = Lx LOW,
1 = Lx HIGH)
L2WU
0 or 1
L1WU
0 or 1
L0WU
0 or 1
Notes
59.
WUR status bits have two functions. After 33742 wake-up,
they indicate the wake up source; for example, L2WU set at 1
if wake-up source is L2 input. After 33742 wake-up and once
the WUR register
has been read, status bits indicate the real-
time state of the Lx inputs (1 = Lx is above threshold, 0 = Lx
input is below threshold). If after a wake-up from Lx input a
watchdog timeout occurs before the first reading of the WUR
register, the LxWU bits are reset. This can occur only if the
33742 was in Stop Mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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