參數(shù)資料
型號(hào)： MC33591FTA
廠商： MOTOROLA INC
元件分類： 消費(fèi)家電
英文描述： PLL Tuned UHF Receiver for Data Transfer Applications
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP24
封裝： PLASTIC, LQFP-24
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 699K
代理商： MC33591FTA
RECEIVER FUNCTIONAL DESCRIPTION
4
MC33591 Technical Data
MOTOROLA
RECEIVER FUNCTIONAL DESCRIPTION
The basic functionality of the ROMEO2 receiver may be seen by reference to the accompanying block
diagram (see figure 1). It is fully compatible with the TANGO3 transmitter.
The RF section comprises a mixer with image cancelling, followed by an IF band-pass filter at 660kHz, an
AGC controlled gain stage and OOK/FSK demodulators, the desired modulation type being selectable by the SPI
interface. The data output from the circuit may either be the data comparator output, or, if Data Manager is
enabled, the SPI port.
The local oscillator is controlled with a PLL referenced to the crystal oscillator. The received channel is defined
by the choice of the crystal frequency.
An SPI bus permits programming the modulation type, data rate, UHF frequency, ID word etc., though to
accomodate applications where no bus interface is available the circuit defaults at power-on to a standard
operating mode.
Depending upon the configuration, the circuit can be either externally strobed by the STROBE input or
internally wait-and-sleep cycled to reduce the power consumption. At any time, a high level on STROBE
overrides the internal timer output and wakes up ROMEO2. When the circuit is switched into sleep mode its
current consumption is approximately 100μA. The circuit configuration which has previously been programmed is
retained.
THE LOCAL OSCILLATOR PLL
The PLL is tuned by comparing the local oscillator frequency, after suitable division, with that of the crystal
oscillator reference. The loop filter has been integrated in the IC. Practical limits upon the values of components
which may be integrated mean that the local oscillator performance may be slightly improved by using an
external PFD filter, shown in Figure 2. In this way the user may choose to have optimum performance with the
addition of external filter components. The PLL gain may be programmed by bit PG: it is recommended that this
bit be set to 1, corresponding to low loop gain.
Figure 2 : External loop filter
C1=4.7nF, C2=390pF, R=1k
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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