MC33567
http://onsemi.com
5
Sense:
If the load is located away from the regulator, the voltage
drop on the connecting cable or trace can become
significant. The MC33567 provides tight voltage load
regulation with varying load currents using its SENSE
feature. As shown in Figure 5, the MC33567 senses the
voltage at the load and provides feedback to the regulator.
The regulator voltage is then adjusted to compensate for the
load changes. It is recommended that the SENSE connection
be placed as close as possible to the load. Also, use a separate
trace to connect the source of the Nchannel MOSFET to the
load to avoid interference or coupling with the SENSE
signal. The use of the SENSE feature is required for correct
device operation. If the SENSE pin is not connected to the
load, the output will go into Hiccup mode.
The current into the SENSE pin is given by the following
equation:
I
SENSE
+ 100 mA )
V
out
1.8 kW
Figure 5. Voltage Regulation Using Sense Feature
SENSE
V
in
R
L
DRV
Feedback
to
Regulator
1.8 kW   V
OUT
+
100 mA
I
SENSE
NChannel MOSFET Selection:
The     MC33567     was     characterized     using
ON Semiconductors MTD3055VL Nchannel MOSFET.
Other MOSFETs can be used with the MC33567 as long as
power and stability requirements are met.
Power:
A MOSFET with a low drainsource on resistance
(R
DS(on)
) will insure the output voltage is not drastically
reduced due to excessive voltage drop across the MOSFET.
The required R
DS(on)
can be calculated using the equation
below:
R
DS(on)
v 0.5
V
in
* V
out
I
LOAD
where:
V
in
= Input Voltage, typically 3.3 V
V
out
= Regulator Output Voltage
(1.2 V, 1.515 V, 1.818 V, 2.3 V, or 2.525 V)
I
LOAD
= Load Current
A safety margin of 0.5 was added to account for R
DS(on)
variations over the operating temperature range.
Stability:
After evaluating the regulator, driver and load system
using control theory it is demonstrated that the output
capacitor, external driver gain and error amplifier gain
bandwidth play an important role on the system stability. To
insure system stability the following set of design guidelines
should be followed:
C
i
+ C
gs
) C
gd
w
f
+
1
C
i
?R
o
w
p
+
1
w
1
)
1
w
f
* 1
1
20 ?/DIV>
1 )
w
a
(3 ?w
p
)
?/DIV>
1
g
m
v R
s
v
(3 ?w
p
)
w
a
?/DIV>
1
g
m
C
o
?R
s
w 5 ?/DIV>
1
w
a
)
1
w
p
where:
w
f
=  Driver pole frequency
C
i
=  Input and reverse transfer capacitance when device
is off
R
o
=  Regulator output resistance (50 W for the MC33567)
w
p
=  Secondary pole for open loop
w
a
=  Error amplifier gain bandwidth
w
1
=  Error amp second pole (set w
1
= w
a
, if not specified)
R
s
=  Output capacitor ESR
g
m
=  Maximum driver transconductance gain
C
o
=  Output capacitance
T   =  Overall loop response time
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