MC33560
http://onsemi.com
13
card extraction). The communication session is terminated
in a given sequence defined in ISO7816–3.
The MC33560 then goes into active mode, in which its
status can be polled.
Stand by mode is reached by deselecting the MC33560
(
CS
=
H
).
FUNCTIONAL BLOCKS
CARD DETECTOR
This block monitors the card contact
CRDDET
(during
insertion and extraction), filters the incoming waveform and
generates an interrupt signal
INT
after each change. In order
to identify which coupler activated the
INT
line
(multicoupler application) the microcontroller scans both
circuits via
CS
and reads the
RDYMOD
pin.
The programming input
CRDCON
tells the level detector
which type of mechanical contact is implemented (normally
open or normally closed). Special care is taken to hold the
current consumption very low on this part of the circuit
which is continuously powered by the
VBAT
supply.
The
CRDDET
pin has high impedance input, and an
external resistor must be connected to pull–up or pull– down,
depending on
CRDCON
. This resistor is chosen according to
the maximum leakage current of the card connector and the
PCB.
The card detector has an internal 50
μ
s debouncing delay.
The micro controller has to insert an additional delay (in the
ms range) to allow the card contacts to stabilize in the card
connector before setting
PWRON
=
H
.
When the card detector circuit detects a card extraction, it
activates the power–down sequence and stops the converter,
regardless of the
PWRON
signal. The 50
μ
s delay of the
debouncer is enough to ensure that all card signals have
reached a safe value before communication with the card
takes place.
CARD STATUS
The controlling microprocessor is informed of the
MC33560 status by interrupt and by polling. When a card is
extracted or inserted, the
INT
line is asserted low. The
interrupt is cleared upon the rising edge of
CS
or upon the
rising edge of
PWRON
(
INT
line set to high state).
The microprocessor can poll the status at any time by
reading the
RDYMOD
pin with proper
PWRON
setting
(see tables 2 and 4 ).
Since
INT
and
RDYMOD
have a high value pull–up
resistor (240
k
typ.), their rise time can be as long as 10
μ
s
if parasitic capacitance is high and no other pull–up circuitry
is connected.
POWER MANAGER
The task of the power manager is to activate only those
circuit functions which are needed for a determined operating
mode in order to minimize power consumption (see figure
19).
In stand by mode
(
PWRON
=
L
) the power manager keeps
only the ”card present” detector alive. All card interface pins
are forced to ground potential.
In the event of a power–up request from the
microcontroller
(
PWRON L
to
H
transition,
CS
=
L
) the
power manager starts the DC/DC converter. As soon as the
CRDVCC
supply reaches the operating voltage range, the
circuit activates the card signals in the following sequence:
CRDVCC, CRDIO, CRDCLK, CRDC4/C8, CRDRST
At the end of the transaction
(
PWRON
reset to
L
,
CS=L
)
or forced card extraction, the
CRDVCC
supply powers
down and the card signal deactivation sequence takes place:
CRDRST, CRDC4/C8, CRDCLK, CRDIO, CRDVCC
When
CS
=
L
, the bi–directional signal lines
(
I
O
,
C4
and
C8
) are put into high impedance state to avoid signal
collision with the microcontroller in transmission mode.
BATTERY UNDERVOLTAGE DETECTOR
The task of this block is to monitor the supply voltage, and
to allow operation of the DC/DC converter only with valid
voltage (typically 1.5 V). The comparator has been designed
to have stability better than 20mV in the temperature range.
DC/DC CONVERTER
Upon request from the power manager, the DC/DC
converter generates the
CRDVCC
supply for the smartcard.
The output voltage is programmable for 3V or 5V (see table
3) to guarantee full cross compatibility of the reader for 5V
and 3V smartcards. The wide voltage supply range, 1.8V <
VBAT
< 6.6V, accommodates a broad range of coupler
applications with different battery configurations (single
cell or multiple cells, serial or parallel connections).
The
CRDVCC
is
short–circuit–proof.To avoid excessive battery loading
during a card short–circuit, a current integration function
forces the power–down sequence (see figure 28). To retry
the session, the microprocessor works through the power on
sequence as defined in the power manager section.
DC/DC Converter operating principles
The DC/DC converter architecture used in the MC33560
allows step–up and step–down voltage conversion to be
done. The unique regulation architecture permits an
automatic transition from step–up to step–down, and from
zero to full load, without affecting the output characteristics.
DC/DC
Converter
Description:
architecture is very similar to the boost architecture, with an
active rectifier in place of the diode. The switching transistor
is connected to ground through a resistor network in order to
adjust the maximum peak current (see figure 22). A transistor
connected to the converter output
(
CRDVCC
) forces this pin
to a low voltage when the converter is not operating. This
prevents erratic voltage supply to the smartcard when not in
use.
current–limited
and
The
converter