參數(shù)資料
型號: MC33298DWR2
廠商: Freescale Semiconductor
文件頁數(shù): 27/28頁
文件大?。?/td> 0K
描述: IC OCTAL SERIAL SWITCH 24-SOIC
標準包裝: 1
類型: 低端
輸入類型: SPI
輸出數(shù): 8
導通狀態(tài)電阻: 350 毫歐
電流 - 輸出 / 通道: 1A
電流 - 峰值輸出: 4A
電源電壓: 9 V ~ 26.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 剪切帶 (CT)
其它名稱: MC33298DWCT
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
33298
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5V
VDD 5.5V, 9.0V VPWR 16V, -40°C TA 125°C, unless otherwise noted.
Typical values noted reflect the approximate value with VPWR = 13V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
Over-temperature Shutdown (Outputs OFF)(22)
TLIM
155
170
185
°C
Over-temperature Shutdown Hysteresis(22)
TLIM(HYS)
10
20
°C
DIGITAL INTERFACE
Input Logic High Voltage(23)
VIH
0.7
1.0
VDD
Input Logic Low Voltage(24)
VIL
0
0.2
VDD
Input Logic Voltage Hysteresis(25)
VI(HYS)
50
100
500
mV
Input Logic Current(26)
IIN
-10
0
10
A
RST Pull-up Current (RST = 0.7VDD)
IRST
10
22
50
A
SFPD Pull-down Current (SFPD = 0.2VDD)
ISFPD
10
22
50
μA
SO High State Output Voltage (IOH = 1.0mA)
VSOH
VDD -1.0V VDD -0.6V
V
SO Low State Output Voltage (IOL = -1.6mA)
VSOL
0.2
0.4
V
SO Tri-state Leakage Current (CS = 0.7VDD, 0V < VSO < VDD)
ISOT
-10
0
10
A
Input Capacitance (0V < VDD < 5.5V)
CIN
12
pF
SO Tri-state Capacitance (0V < VDD < 5.5V)
CSOT
20
pF
Notes
22.
This parameter is guaranteed by design, but it is not production tested.
23.
Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs.
24.
Lower logic threshold voltage range applies to SI, CS, SCLK, Reset, and SFPD input signals.
25.
Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design, but it is not production tested.
26.
Input current of SCLK, SI and CS logic control inputs.
27.
Input capacitance of SI, CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not
production tested.
28.
Tri-state capacitance of SO for 0V < VDD < 5.5V. This parameter is guaranteed by design, but it is not production tested.
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