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參數(shù)資料
| 型號(hào)： | MC14536BDWR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC PROG TIMER 2MHZ 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 可編程計(jì)時(shí)器 |
| 頻率： | 2MHz |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 電源： | 15µA |
| 工作溫度： | -55°C ~ 125°C |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | MC14536BDWR2OSDKR |
MC14536B
http://onsemi.com
8
Figure 8. Power Dissipation Test
Circuit and Waveform
Figure 9. Switching Time Test Circuit and Waveforms
VDD
0.01
mF
CERAMIC
500
mF
ID
CL
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
20 ns
90%
10%
50%
DUTY CYCLE
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
CL
VSS
VDD
20 ns
50%
IN1
tWL
tWH
50%
tPHL
90%
10%
tPLH
tTLH
tTHL
OUT
FUNCTIONAL TEST SEQUENCE
Test function (Figure 10) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8stage sections and 255 counts are loaded in each of the
8stage sections in parallel. All flipflops are now at a “1”.
The counter is now returned to the normal 24stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
Figure 10. Functional
Test Circuit
VDD
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
In1
Set
Reset
8Bypass
Decade Out
Q1 thru Q24
All 24 stages are in Reset mode.
1
0
1
0
1
0
Counter is in three 8 stage sections in parallel mode.
0
1
0
First “1” to “0” transition of clock.
1
0
1
255 “1” to “0” transitions are clocked in the counter.
0
1
The 255 “1” to “0” transition.
0
1
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
1
In1 Switches to a “1”.
0
Counter Ripples from an all “1” state to an all “0” state.
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