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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 49/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
49
MOTOROLA RF/IF DEVICE DATA
It is noted that the results obtained from the simulation
compare favorably to those obtained from the measurements
of the EVK. The simulation display resolution is adjusted to
represent the same
±
4 kHz deviation as shown in Figure 53.
Since variation in VCO control voltage is equal to the VCO
frequency divided by the VCO gain, this axis may be
redefined to show change in frequency rather than change in
control voltage.
The models shown represent a “skeleton” that may be
used to develop extensive and reliable simulations that can
greatly reduce actual breadboarding and testing. In addition
to the basic simulations shown, PSpice provides a method by
which worst case and Monte Carlo evaluation can be
performed on all, or selected components. By limiting the
circuit to minimum necessary components, simulation can be
performed using only the PSpice evaluation copy. In addition,
the optional PSpice program Optimizer should allow refining
the loop filter more easily.
While PSpice is a powerful tool, it is not without limits.
Since it was designed to run on large mainframe computers,
the PC is just now becoming powerful enough to make use of
the capability of the simulator. A fast Pentium class processor
with a large RAM and a hard drive of the Gbyte size is a
necessity. Even with the most judicious planning, some
simulations will “bump” the limits of the system.
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