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參數(shù)資料
| 型號(hào)： | MC145170-2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer With Serial Interface(帶串行口的PLL頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器的串行接口（帶串行口的鎖相環(huán)頻率合成器） |
| 文件頁(yè)數(shù)： | 10/26頁(yè) |
| 文件大?。?/td> | 373K |
| 代理商： | MC145170-2 |
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MC145170–2
10
MOTOROLA RF/IF DEVICE DATA
Frequency of fV > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: negative
pulses from high impedance
Frequency and Phase of fV = fR: essentially
high–impedance state; voltage at pin determined by loop
filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the
high–impedance state by utilization of the disable feature in
the C register (patented).
φ
R and
φ
V
Double–Ended Phase/Frequency Detector Outputs
(Pins 14, 15)
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR:
φ
V =
negative pulses,
φ
R = essentially high
Frequency of fV < fR or Phase of fV Lagging fR:
φ
V =
essentially high,
φ
R = negative pulses
Frequency and Phase of fV = fR:
φ
V and
φ
R remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR:
φ
R =
negative pulses,
φ
V = essentially high
Frequency of fV < fR or Phase of fV Lagging fR:
φ
R =
essentially high,
φ
V = negative pulses
Frequency and Phase of fV = fR:
φ
V and
φ
R remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and
interchanged via the C register (patented).
LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies (see Figure
17).
This output can be enabled and disabled via the C register
(patented). Upon power up, on–chip initialization circuitry
disables LD to a static low logic level to prevent a false “l(fā)ock”
signal. If unused, LD should be disabled and left open.
POWER SUPPLY
VDD
Most Positive Supply Potential (Pin 16)
This pin may range from 2.7 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to
VSS using low–inductance capacitor(s) mounted very close
to the device. Lead lengths on the capacitor(s) should be
minimized. (The very fast switching speed of the device
causes current spikes on the power leads.)
VSS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes,
the VSS pin is tied to a ground plane.
ENB
CLK
Din
Power
Up
1
2
3
4 or More Clocks
5
1
2
3
4
NOTE:
This initialization sequence is usually not necessary because the on–chip power–on reset circuit performs the initialization
function. However, this initialization sequence must be used immediately after power up if control of the CLK pin is not
possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below
2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the on–chip
power–on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V.
Don’t Cares
Don’t Cares
One
Zeroes
Zero
Figure 13. Reset Sequence
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PDF描述 |
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| MC145170 | PLL Frequency Synthesizer(PLL頻率發(fā)生器) |
| MC14517BCL | Dual 64-Bit Static Shift Register |
| MC14517 | Dual 64-Bit Static Shift Register |
| MC14517BDWR2 | Dual 64-Bit Static Shift Register |
| MC14517BCP | Non-inverting High Speed MOSFET Driver with Active Pullup and Internal Regulator 5-SOT-23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145170D1 | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| MC145170D2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170D2R2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2R2 | 功能描述:IC SERIAL PLL FREQ SYNTH 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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