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參數(shù)資料
型號: MC145151DW2R2
廠商: Freescale Semiconductor
文件頁數(shù): 15/24頁
文件大?。?/td> 0K
描述: IC PAR-IN PLL FREQ SYNTH 28-SOIC
標準包裝: 1,000
類型: PLL 時鐘/頻率合成器
PLL:
輸入: 時鐘
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 25MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 9 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
其它名稱: MC145151DW2TR
MC145151-2 and MC145152-2 Technical Data, Rev. 5
22
Freescale Semiconductor
Design Considerations
For the maximum frequency into the prescaler (fVCOmax), the value used for P must be large enough such
that:
1. fVCOmax divided by P may not exceed the frequency capability of fin (input to the ÷ N and ÷ A
counters).
2. The period of fVCO divided by P must be greater than the sum of the times:
a) Propagation delay through the dual-modulus prescaler.
b) Prescaler setup or release time relative to its MC signal.
c) Propagation time from fin to the MC output for the frequency synthesizer device.
A sometimes useful simplification in the programming code can be achieved by choosing the values for P
of 8, 16, 32, or 64. For these cases, the desired value of NT results when NT in binary is used as the program
code to the
÷ N and ÷ A counters treated in the following manner:
1. Assume the
÷ A counter contains “a” bits where 2a ≥ P.
2. Always program all higher order
÷ A counter bits above “a” to 0.
3. Assume the
÷ N counter and the ÷ A counter (with all the higher order bits above “a” ignored)
combined into a single binary counter of n + a bits in length (n = number of divider stages in the
÷ N counter). The MSB of this “hypothetical” counter is to correspond to the MSB of ÷ N and the
LSB is to correspond to the LSB of
÷ A. The system divide value, N
T, now results when the value
of NT in binary is used to program the “new” n + a bit counter.
By using the two devices, several dual-modulus values are achievable.
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