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參數(shù)資料
| 型號： | MC14490P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Digital Signal Processor 196-CFP -55 to 125 |
| 中文描述： | 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 265K |
| 代理商： | MC14490P |
MOTOROLA CMOS LOGIC DATA
MC14490
302
TYPICAL APPLICATIONS
ASYMMETRICAL TIMING
In applications where different leading and trailing edge
delays are required (such as a fast attack/slow release
timer.) Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be inter-
changed. The clock out lead can then be used to feed clock
signals to the other MC14490 packages where the asym-
metrical input/output timing is required.
Figure 6. Fast Attack/Slow Release Circuit
IN
OUT
OSCout
MC14011B
OSCin
A
B
fC/N
EXTERNAL
CLOCK
÷
N
fC
MC14490
LATCHED OUTPUT
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
Figure 7. Latched Output Circuit
IN
OUT
OSCout
MC14011B
OSCin
MC14490
CLOCK
LATCH = 1
UNLATCH = 0
MULTIPLE TIMING SIGNALS
As shown in Figure 8, the Bounce Eliminator circuits can
be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where it
is required to have a single pulse output for a single opera-
tion (make) of the push button or relay contact. This only
requires the series connection of two Bounce Eliminator cir-
cuits, one inverter, and one NOR gate in order to generate
the signal AB as shown in Figures 9 and 10. The signal AB is
four clock periods in length. If the inverter is switched to the A
output, the pulse AB will be generated upon release or break
of the contact. With the use of a few additional parts many
different pulses and waveshapes may be generated.
Figure 8. Multiple Timing Circuit Connections
10
5
12
3
14
1
7
9
6
11
4
13
2
15
Aout
Bout
Cout
Dout
Eout
Fout
OSCin
CLOCK
B.E. 6
B.E. 5
B.E. 4
B.E. 3
B.E. 2
B.E. 1
OSCout
Ain
Bin
Cin
Din
Ein
Fin
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