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參數(shù)資料
| 型號： | MC14489P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Digital Signal Processor 181-CPGA -55 to 125 |
| 中文描述： | LED DISPLAY DRIVER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 303K |
| 代理商： | MC14489P |
MC14489
4
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(TJ = – 40
°
to 130
°
C*, CL = 50 pF, Input tr = tf = 10 ns)
Symbol
Parameter
VDD
V
Guaranteed
Limit
Unit
fclk
Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock tw below
(Figure 1)
3.0
4.5
6.0
dc to 3.0
dc to 4.0
dc to 4.0
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5)
3.0
4.5
6.0
140
80
80
ns
tTLH,
tTHL
Maximum Output Transistion Time, Data Out
(Figures 1 and 5)
3.0
4.5
6.0
70
50
50
ns
fR
Refresh Rate — Bank 1 through Bank 5
(Figures 2 and 6)
3.0
4.5
6.0
NA
700 to 1900
700 to 1900
Hz
Cin
Maximum Input Capacitance — Data In, Clock, Enable
—
10
pF
* See Thermal Considerations section.
TIMING REQUIREMENTS
(TJ = – 40
°
to 130
°
C*, Input tr = tf = 10 ns unless otherwise indicated
)
Symbol
Parameter
VDD
V
Guaranteed
Limit
Unit
tsu, th
Minimum Setup and Hold Times, Data In versus Clock
(Figure 3)
3.0
4.5
6.0
50
40
40
ns
tsu, th,
trec
Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4)
3.0
4.5
6.0
150
100
100
ns
tw(L)
Minimum Active–Low Pulse Width, Enable
(Figure 4)
3.0
4.5
6.0
4.5
3.4
3.4
μ
s
tw(H)
Minimum Inactive–High Pulse Width, Enable
(Figure 4)
3.0
4.5
6.0
300
150
150
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
3.0
4.5
6.0
167
125
125
ns
tr, tf
Maximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1)
3.0
4.5
6.0
1
1
1
ms
*See Thermal Considerations section.
**For a high–speed 8–Clock access, th for Enable is determined as follows:
VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 – (7500/fclk)
VDD = 4.5 to 6 V, fclk > 2.34 MHz: th = 3300 – (7500/fclk)
where th is in ns and fclk is in MHz.
NOTES:
1. This restriction does NOT apply for fclk rates less than those listed above. For “slow” fclk rates, use the th limits in the above table.
2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
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| MC14490DW | 功能描述:算數(shù)邏輯單元 - ALU LOG CMOS 3-18V HEX BOUNCE ELIMINATOR RoHS:否 制造商:ON Semiconductor 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:18 V 電源電壓-最小:3 V 封裝 / 箱體:SOIC-16 Wide 最大工作溫度:+ 125 C 封裝:Reel |
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| MC14490DWR2 | 功能描述:算數(shù)邏輯單元 - ALU LOG CMOS 3-18V HEX BOUNCE ELIMINATOR RoHS:否 制造商:ON Semiconductor 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:18 V 電源電壓-最小:3 V 封裝 / 箱體:SOIC-16 Wide 最大工作溫度:+ 125 C 封裝:Reel |
| MC14490DWR2G | 功能描述:算數(shù)邏輯單元 - ALU LOG CMOS 3-18V HEX BOUNCE ELIMINATOR RoHS:否 制造商:ON Semiconductor 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:18 V 電源電壓-最小:3 V 封裝 / 箱體:SOIC-16 Wide 最大工作溫度:+ 125 C 封裝:Reel |
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