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參數(shù)資料
| 型號： | MC14415VL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | Digital Signal Processors 68-CPGA -55 to 125 |
| 中文描述： | SPECIALTY LOGIC CIRCUIT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MC14415VL |
MOTOROLA CMOS LOGIC DATA
293
MC14415
Figure 2. Typical Operation Modes and Functional Timing Diagram
Mode 1: OUTPUT SET Initiates Time Delay
Mode 2: Set A Initiates Time Delay
Mode 4: Positive–Edge Strobe (ST2)
Initiates Time Delay
Mode 3: OUTPUT INHIBIT Disables Time Delay
INPUT DISABLE
STROBE 2
STROBE 1
SET A
OUTPUT SET
OUTPUT INHIBIT
CLOCK
OUTPUT A
50%
50%
50%
tPLH
tPHL
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
100
2
1
INPUT DISABLE
STROBE 2
STROBE 1
SET A
OUTPUT SET
OUTPUT INHIBIT
CLOCK
OUTPUT A
50%
50%
100
2
1
tPLH
tPHL
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
INPUT DISABLE
STROBE 2
STROBE 1
SET A
OUTPUT SET
OUTPUT INHIBIT
CLOCK
OUTPUT A
tPLH
tPHL
tPLH
tPHL
100
2
1
50%
50%
INPUT DISABLE
STROBE 2
STROBE 1
SET A
OUTPUT SET
CLOCK
OUTPUT A
1
100
50%
50%
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
tPLH
tPHL
50%
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