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參數(shù)資料
| 型號： | MC14415VL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 標準邏輯 |
| 英文描述： | Digital Signal Processors 68-CPGA -55 to 125 |
| 中文描述： | SPECIALTY LOGIC CIRCUIT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MC14415VL |
MOTOROLA CMOS LOGIC DATA
291
MC14415
VDD
(No Load)
10
—
0.01
—
0
0.01
—
0.05
“1” Level
VOH
5.0
15
—
—
—
—
3.0
—
4.14
14.12
—
—
—
—
—
—
Vdc
Noise Immunity
(
Vout
4.5 Vdc)
15
—
—
—
6.75
—
—
—
Vdc
5.0
1.4
—
1.5
2.25
—
1.5
—
Vdc
(
1.5 Vdc)
(IOH = 0 mA)
(IOH = 15 mA)
Source
5.0
10
—
—
—
—
—
—
—
—
—
—
—
—
3.0
2.7
2.2
8.0
7.7
7.1
4.14
3.44
3.08
9.09
8.45
8.14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vdc
(IOH = 15 mA)
15
—
—
—
—
—
—
—
—
—
14.12
13.81
13.61
—
—
—
—
—
—
—
—
—
Vdc
Output Drive Current
(VOL = 0.4 Vdc)
Input Leakage Current
Sink
5.0
15
0.23
—
—
—
0.2
—
0.78
7.8
—
—
0.16
—
—
—
mAdc
15
—
±
0.3
—
±
0.00001
±
0.3
—
±
1.0
μ
Adc
Input Capacitance
—
—
—
—
5.0
—
—
—
pF
Quiescent Dissipation
PQ
5.0
15
—
—
0.25
—
—
—
0.00005
0.00050
0.25
—
—
—
3.5
—
mW
Power Dissipation**
**The formulas given are for the typical characteristics only.
5.0
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
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