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參數(shù)資料
| 型號(hào)： | MC144111DWR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC QUAD SERIAL D/A CONV 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 6 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 50mW |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | MC144111DWTR |
MC144110 Technical Data, Rev. 2
8
Freescale Semiconductor
Pin Descriptions
4
Pin Descriptions
4.1
INPUTS
Din
Data Input
Six-bit words are entered serially, MSB first, into digital data input, Din. Six words are loaded into the
MC144110 during each D/A cycle; four words are loaded into the MC144111.
The last 6-bit word shifted in determines the output level of pins Q1 Out and R1 Out. The next-to-last 6-bit
word affects pins Q2 Out and R2 Out, etc.
ENB
Negative Logic Enable
The ENB pin must be low (active) during the serial load. On the low-to-high transition of ENB, data
contained in the shift register is loaded into the latch.
CLK
Shift Register Clock
Data is shifted into the register on the high-to-low transition of CLK. CLK is fed into the D-input of a
transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high.
The number of clock cycles required for the MC144110 is usually 36. The MC144111 usually uses 24
cycles. See Table 4 for additional information.
4.2
OUTPUTS
Dout
Data Output
The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage.
R1 Out through Rn Out
Resistor Network Outputs
These are the R-2R resistor network outputs. These outputs may be fed to high-impedance input FET op
amps to bypass the on-chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 k
.
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