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參數(shù)資料
| 型號： | MC12439FNR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 128K |
| 代理商： | MC12439FNR2 |
4
MC12439
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
393
Figure 2. Timing Diagram
S_CLOCK
S_DATA
S_LOAD
M[6:0]
N[1:0]
P_LOAD
T2
T1
T0
N1
N0 M6 M5 M4 M3 M2 M1
M0
M, N
First
Bit
Last
Bit
Figure 3. Serial Test Clock Block Diagram
FDIV4
MCNT/2
LOW
FOUT
MCNT/2
FREF
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N DIVIDE
(1, 2, 4, 8)
0
1
PLL 12439
LATCH
Reset
PLOADB
M COUNTER
SLOAD
T0
T1
T2
VCO
SHIFT
REG
12-BIT
DECODE
SDATA
SCLOCK
MCNT
FREF
SEL_CLK
T2 = T1 = 1, T0 = 0: Test Mode (PLL Bypass)
SCLOCK is selected, MCNT/2 is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Shift Reg Out
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