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參數(shù)資料
| 型號： | MC12439FNR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 128K |
| 代理商： | MC12439FNR2 |
4
MC12439
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
398
that as with the other modes, the jitter improves with increasing
frequency. The
±65 ps shown in the data sheet table represents
a conservative value of jitter, especially for the higher VCO, and
thus output frequencies.
Figure 8. Peak–to–Peak Jitter versus
Output Frequency
40
60
80
100
120
140
400
500
600
700
800
Spec Limit
N=1
Output Frequency (MHz)
Peak-to-Peak
Jitter
(ps)
The jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most system
designs while adding the flexibility of frequency margining and
field upgrades. These features are not available with a fixed
frequency SAW oscillator.
Output Voltage Swing vs Frequency
In the divide by one mode, the output rise and fall times will
limit the peak to peak output voltage swing. For a 400 MHz
output, the peak to peak swing of the 12439 output will be
approximately 700 mV. This swing will gradually degrade as the
output frequency increases, at 800 MHz the output swing will be
reduced to approximately 500 mV. For a worst case analysis, it
would be safe to assume that the 12439 output will always
generate at least a 400mV output swing. Note that most high
speed ECL receivers require only a few hundred millivolt input
swings for reliable operation. As a result, the output generated
by the 12439 will, under all conditions, be sufficient for clocking
standard ECL devices. Note that if a larger swing is desired, the
MC12439 could drive the clock fanout buffer MC100EP111.
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