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參數(shù)資料
| 型號： | MC12206D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 145K |
| 代理商： | MC12206D |
MC12206
MOTOROLA
HIPERCOMM
BR1334 — Rev 4
8
Figure 6. Detailed Phase Comparator Block Diagram
PHASE
FREQUENCY
DETECTOR
R
V
UP
DOWN
PHASE COMPARATOR
1
0
1
0
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LD
φ
R
φ
P
fr
fp
FC
LE
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally
HIGH. LD is designed to be the logical NORing of the phase frequency detector’s outputs UP and DOWN. See Figure 6. In typical
applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through
a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be
between 500 and 2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal
amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the
internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be
connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper
crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a
maximum of 30 pF each including parasitic and stray capacitance).
DUAL INTERNAL CHARGE PUMPS
(“ANALOG SWITCH”)
Due to the pure Bipolar nature of the MC12206 design, the “analog switch” function is implemented with dual internal charge
pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output
BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin,
and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is
LOW, BISW is in a high impedance state and Do output is active.
Figure 7. “Analog Switch” Block Diagram
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LE
LPF–1
LPF–2
VCO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC12206DT | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer |
| MC1220DIN | 功能描述:電源線濾波器 Filter 250V 20A RoHS:否 制造商:EPCOS 電壓額定值:277 VAC 電流額定值:100 A 安裝風(fēng)格:Chassis 端接類型:Screw |
| MC1220DIN-HFP | 制造商:TDK-Lambda Corporation 功能描述:FILTER250V (AC,,DC,)20A,3.8" X 2.36" X 1.36", HAZMAT - Bulk |
| MC1220F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC1220-HFP | 制造商:TDK-Lambda Corporation 功能描述:FILTER250V (AC,,DC,)20A,3.8" X 2.36" X 1.36", HAZMAT - Bulk |
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