參數(shù)資料
型號(hào): MC12206D
廠商: MOTOROLA INC
元件分類: XO, clock
英文描述: MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16
封裝: PLASTIC, SO-16
文件頁數(shù): 6/12頁
文件大?。?/td> 145K
代理商: MC12206D
MC12206
MOTOROLA
HIPERCOMM
BR1334 — Rev 4
6
PHASE CHARACTERISTICS/VCO CHARACTERISTICS
The phase comparator in the MC12206 is a high speed digital phase frequency detector circuit. The circuit determines the “l(fā)ead”
or “l(fā)ag” phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input.
Since these edges occur only once per cycle, the detector has a range of
±
2
π
radians. The phase comparator outputs are
standard CMOS rail–to–rail levels (VP to GND for
φ
P and VCC to GND for
φ
R), designed for up to 20MHz operation into a 15pF
load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics.
The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are
controlled by the FC pin. The polarity of the phase comparator outputs,
φ
R and
φ
P, as well as the charge pump output Do can be
reversed by switching the FC pin.
Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms
fr
fp
LD
Do (FC = H)
BISW (LE = H or Open)
φ
R (FC = H)
φ
P (FC = H)
Do (FC = L)
BISW (LE = H or Open)
φ
R (FC = L)
φ
P (FC = L)
H
L
H
L
H
L
Source
Z
Sink
H
L
H
L
Source
Z
Sink
H
L
H
L
NOTES: Do and BISW are current outputs.
Phase difference detection range: –2
π
to +2
π
Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
Internal Charge Pump Gain
Isource
Isink
4
4mA
4
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