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參數(shù)資料
| 型號(hào)： | MC10EP14DT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 10E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | MC10EP14DT |
1
Motorola, Inc. 1999
Product Preview
1:5 Clock Distribution Chip
475ps Typical Propagation Delay
50ps Output–to–Output Skew
PECL mode: 3.0V to 5.5V VCC with VEE = 0V
ECL mode: 0V VCC with VEE = –3.0V to –5.5V
Synchronous Enable/Disable
Multiplexed Clock Input
Internal Input Resistors: Pulldown on D, D
Q Output will default LOW with inputs open or at VEE
ESD Protection: >4KV HBM, >200V MM
Maximum Frequency > 2.7GHz
VBB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
Transistor Count = TBD devices
Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
The MC10EP14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution ap-
plications. The device can be driven by either a differential or single–ended ECL or, if positive power supplies are used,
PECL input signal. The EP14 is functionally and pin compatible with the EL14 and LVEL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of –3.0V to –5.5V (or 3.0V to 5.5V). If a single–ended input is to be
used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB
output is designed to act as the switching reference for the input of the EP14 under single–ended input conditions.
The EP14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL
pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in
the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can
happen with an asynchronous control. The internal flip–flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of the clock input.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA
Semiconductor Components
Order Number: MC10EP14/D
Rev. 0.2, 06/1999
MC10EP14
PIN
FUNCTION
CLK/CLK
ECL Diff Clock Inputs
SCLK
ECL Scan Clock Input
EN
ECL Sync Enable
SEL
ECL Clock Select Input
VBB
ECL Reference Output
Q0–Q4/Q0–Q4 ECL Diff Outputs
PIN DESCRIPTION
SO–20, DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E
TRUTH TABLE
CLK
SCLK
SEL
EN
Q
LX
L
HX
L
H
XL
H
L
XH
H
L
H
XX
X
H
L*
ORDERING INFORMATION
MC10EP14DT
TSSOP
* On next negative transition of CLK or SCLK
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