- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄29119 > MC10EP196FAR2 (ON SEMICONDUCTOR) ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MC10EP196FAR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 延遲線 |
| 英文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 120K |
| 代理商： | MC10EP196FAR2 |
Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 4
1
Publication Order Number:
MC10EP196/D
MC10EP196, MC100EP196
Product Preview
3.3V/5VECL Programmable
Delay Chip with FTUNE
The MC10/100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It is identical to the
EP195 with the exception of the added feature of further tuneability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a
range of up to 10.2 ns. The required delay is selected by 10 data select
inputs D[0:9] which are latched on chip by a high signal on the latch
enable (LEN) control. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 1,
Table 2, and Figure 3.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.2 ns. An additional pin, D10, is provided for
cascading multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs.
Select input pins, D0–D10, may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8) for
CMOS, ECL, or TTL level signals. For CMOS input levels, leave VCF
and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8). For
TTL level operation, connect a 1.5 V supply reference to VCF and leave
open VEF pin. The 1.5 V reference voltage to VCF pin can be
accomplished by placing a 1.5 k
W or 500 W resistor between VCF and
VEE for 3.3 V or 5.0 V power supplies, respectively.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single–ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01
mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Maximum Frequency > 1.8 GHz Typical
PECL Mode Operating Range: V
CC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: V
CC = 0 V
with VEE = –3.0 V to –5.5 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic Low
V
BB Output Reference Voltage
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
32
1
MCXXX
AWLYYWW
EP196
Device
Package
Shipping
ORDERING INFORMATION
MC10EP196FA
LQFP–32
250 Units/Tray
MC10EP196FAR2
LQFP–32
2000 Tape & Reel
LQFP–32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
XXX = 10 OR 100
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
*For additional information, refer to Application Note
AND8002/D
MC100EP196FA
LQFP–32
250 Units/Tray
MC100EP196FAR2
LQFP–32
2000 Tape & Reel
http://onsemi.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC10H104L | 10H SERIES, QUAD 2-INPUT AND GATE, CDIP16 |
| MC10H104MR2 | 10H SERIES, QUAD 2-INPUT AND GATE, PDSO16 |
| MC10H117P | 10H SERIES, DUAL 5-INPUT OR-AND/OR-AND-INVERT GATE, PDIP16 |
| MC10H121FNR2 | 10H SERIES, 11-INPUT OR-AND/OR-AND-INVERT GATE, PQCC20 |
| MC10H135FNR2 | 10H SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10EP29DT | 功能描述:觸發(fā)器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC10EP29DTG | 功能描述:觸發(fā)器 3.3V/5V ECL Dual D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC10EP29DTR2 | 功能描述:觸發(fā)器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC10EP29DTR2G | 功能描述:觸發(fā)器 3.3V/5V ECL Dual D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC10EP29MNG | 功能描述:觸發(fā)器 BBG ECL DL DIFF DFF W/SET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。