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參數(shù)資料
| 型號： | MC10198FNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 諧振器 |
| 英文描述： | 10K SERIES, MONOSTABLE MULTIVIBRATOR, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 154K |
| 代理商： | MC10198FNR2 |
MC10198
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°C
–0.700
–1.825
–1.440
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
6, 8
1, 4, 16
Input Current
IinH
5, 10
13
15
5,10
13
15
6, 8
1, 4, 16
IinL
5
6, 8
1, 4, 16
Output Voltage
Logic 1
VOH
2
3
13 (4.)
13
6, 8
1, 4, 16
Output Voltage
Logic 0
VOL
2
3
13 (4.)
13
6, 8
1, 4, 16
Threshold Voltage
Logic 1
VOHA
2
3
15
6, 8
1, 16, 4
Threshold Voltage
Logic 0
VOLA
2
3
15
6, 8
1, 16, 4
Switching Times
(50
Load)
+1.11V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Trigger Input
tT+Q+
tT–Q+
3
10
5
13
3
6, 8
1, 16, 4
High Speed Trigger Input
tHS+Q+
3
15
3
6, 8
1, 16, 4
Minimum Timing Pulse Width
PWQmin
3
Note 2.
6, 8
1, 16, 4
Maximum Timing Pulse Width
PWQmax
3
Note 3.
6, 8
1, 16, 4
Minimum Trigger Pulse Width
PWT
3
13
3
6, 8
1, 16, 4
Minimum Hi–Spd Trigger Pulse
Width
PWHS
3
15
3
6, 8
1, 16, 4
Rise Time
(20 to 80%)
3
6, 8
1, 16, 4
Fall Time
(20 to 80%)
3
6, 8
1, 16, 4
Enable Setup Time
tsetup (E)
3
5
3
6, 8
1, 16, 4
Enable Hold Time
thold (E)
3
5
3
6, 8
1, 16, 4
1. The monostable is in the timing mode at the time of this test.
2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE).
3. CEXT = 10F (Pin); REXT = 2.7k (Pin 6).
4.
VIHmax
VILmin
P1
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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