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參數(shù)資料
| 型號： | MC10168P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Latch |
| 中文描述： | 10K SERIES, HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 69K |
| 代理商： | MC10168P |
MC10168
MOTOROLA
MECL Data
DL122 — Rev 6
3–100
ELECTRICAL CHARACTERISTICS
Pin
Under
Test
Test Limits
–30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
IinH
8
82
60
75
82
mAdc
Input Current
3,7,9,14
4,5,10,12
13
390
425
460
245
265
290
245
265
290
μ
Adc
IinL
VOH
*
0.5
0.5
0.3
μ
Adc
Output Voltage
Logic 1
2
6
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
6
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
6
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
2
6
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times
(50
Load)
ns
Propagation Delay
Data
Gate
Clock
t3+2+
t5–2+
t13+2+
t3+13+
t13+3+
t2+
t2–
2
2
2
1.0
1.0
1.0
5.6
3.2
5.8
1.0
1.0
1.0
3.0
2.0
4.0
5.4
3.1
5.6
1.1
1.0
1.2
5.9
3.4
6.2
Setup Time
2
2.5
2.5
2.5
Hold Time
2
1.0
1.0
1.0
Rise Time
(20 to 80%)
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
Fall Time
(20 to 80%)
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
* Individually test each input applying VIH or VIL to input under test.
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