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參數(shù)資料
| 型號： | MC10161P |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 10K SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MC10161P |
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10161/D
MC10161
Binary to 1-8 Decoder
(Low)
The MC10161 is designed to decode a three bit input word to a one
of eight line output. The selected output will be low while all other
outputs will be high. The enable inputs, when either or both are high,
force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This design provides the identical 4 ns delay from any address or enable
input to any output.
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1. This system, using the MC10136 control
counters, has the capability of incrementing, decrementing or holding
data channels. When both S0 and S1 are low, the index counters reset,
thus initializing both the mux and demux units. The four binary
outputs of the counter are buffered by the MC10161s to send
twisted–pair select data to the multiplexer/demultiplexer to units.
P
D = 315 mW typ/pkg (No Load)
t
pd = 4.0 ns typ
t
r, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
E0 2
E1 15
A7
B9
C14
6Q0
5Q1
4Q2
3Q3
13Q4
12Q5
11Q6
10Q7
TRUTH TABLE
ENABLE
INPUTS
OUTPUTS
E1
E0
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
H
X
H
X
H
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10161L
CDIP–16
25 Units / Rail
MC10161P
PDIP–16
25 Units / Rail
MC10161FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10161L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10161
AWLYYWW
1
16
MC10161P
AWLYYWW
DIP PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
VCC2
E1
C
Q4
Q5
Q6
Q7
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC10162FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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